Wafer Alignment Mark Scheme

ABSTRACT

A wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No. 15/864,458 which was filed on Jan. 8, 2018, which is a continuation of U.S. patent application Ser. No. 14/486,514 which was filed on Sep. 15, 2014, now U.S. Pat. No. 9,863,754 issue on Jan. 9, 2018, which is a divisional application of U.S. patent application Ser. No. 13/485,224, filed on May 31, 2012, which claims priority of U.S. Provisional Patent Application No. 61/616,975, filed on Mar. 28, 2012, which applications are incorporated herein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates generally to an integrated circuit and more particularly to a wafer alignment mark.

BACKGROUND

For an integrated circuit fabrication process, some wafers have a notch for wafer alignment. For such a wafer, the wafer is rotated 360° in some cases to find the wafer notch for alignment. However, the wafer notch may result in random solvent splash on the wafer during a wafer edge cleaning process, which is a defect source and can induce yield penalty. Also, such solvent splash can induce arcing effect during an etching process of the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1A is a schematic diagram of an exemplary wafer with wafer alignment marks according to some embodiments;

FIG. 1B is a cross-section view of an exemplary wafer with wafer alignment marks according to some embodiments;

FIG. 1C is a schematic diagram of an exemplary wafer alignment mark detection setup according to some embodiments;

FIGS. 2A-2D are plots of detected light intensity versus wafer position for the exemplary wafer alignment marks in FIG. 1A according to some embodiments;

FIG. 3 is a schematic diagram of exemplary wafer alignment mark shapes according to some embodiments; and

FIG. 4 is a flowchart of an exemplary method of wafer aligning using wafer alignment marks in FIG. 1A according to some embodiments.

DETAILED DESCRIPTION

The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use, and do not limit the scope of the disclosure.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

FIG. 1A is a schematic diagram of an exemplary wafer 102 with wafer alignment marks 104 according to some embodiments. The wafer 102 has wafer alignment marks 104 at a backside 103. There are four exemplary wafer alignment marks 104 centered at positions evenly distributed along the edge of the wafer 102 as shown in FIG. 1A: a first wafer alignment mark 104 a having one recess (opening, hole, or cut), a second wafer alignment mark 104 b having two recesses, a third wafer alignment mark 104 c having three recesses, and a fourth wafer alignment mark 104 d having four recesses. The wafer 102 comprises silicon or any other suitable material. The wafer alignment marks 104 are formed on the wafer's backside by laser or etching, for example.

The four wafer alignment marks 104 a, 104 b, 104 c, and 104 d are formed centered at 0°, 90°, 180°, and 270° respectively along the edge of the wafer 102. Therefore, by rotating the wafer 102 by 90°, one of the four wafer alignment marks will be detected to find the alignment position. If a different number of wafer alignment marks 104 are used, the positions of the wafer alignment marks 104 can be evenly distributed by dividing 360° by the number of the wafer alignment marks 104. For example, if there are three wafer alignment marks 104, they can be distributed at 0°, 120°, 240°. In this case, the wafer can be rotated by 120° to find one of the wafer alignment marks 104 to find the alignment position. In other embodiments, the wafer alignment marks 104 can be distributed unevenly depending on the applications.

The size of the wafer alignment marks 104 are from (1 mm×1 mm) to (5 mm×5 mm) in some embodiments. The wafer alignment marks 104 have a depth of 0.12 μm in one example. The shape of the wafer alignment marks 104 can be different shapes, such as a circle, triangle, square or any other polygon, for example.

FIG. 1B is a cross-section view of exemplary wafer 102 with wafer alignment marks 104 according to some embodiments. The wafer 102 has a front side 101 used as a main surface for integrated circuit formation and the backside 103. The wafer alignment marks 104 are formed on the backside 103 of the wafer 102. The wafer 102 has a thickness 106 ranging from 100 μm to 300 μm in some embodiments. The wafer alignment marks 104 (recesses) have a depth 105 ranging from 100 nm to 200 nm in some embodiments. If the depth 105 is less than 100 nm, the detection of the wafer alignment marks 104 may need higher sensitivity to recognize the difference in reflected light intensity due to the wafer alignment marks 104. If the depth 105 is greater than 200 nm, particles may remain in the wafer alignment marks 105.

FIG. 1C is a schematic diagram of an exemplary wafer alignment mark detection setup 107 according to some embodiments. A light source 108 such as laser and a light detection device 110 such as charge-coupled device (CCD) sensor are located under the wafer 102. As the wafer 102 is rotated by a rotation device 112 for a specified angle, light transmitted from the light source 108 is directed to the wafer backside 103 and reflected to the light detection device 110. The light detection device 110 such as a CCD sensor collects the light intensity distribution to find the wafer alignment position. In some embodiments, the detected light intensity is reduced at the wafer alignment mark 104 positions to find the alignment positions.

By using the wafer alignment mark 104 formed on the backside 103 of the wafer 102, solvent splash impact is reduced during the wafer edge cleaning process. With four wafer alignment mark 104 evenly spaced as shown in FIG. 1A, the alignment mark search time (e.g., rotating the wafer 90°) is reduced 75% compared to finding a notch by rotating the wafer 360°. Therefore, the wafer process yield time is improved.

FIGS. 2A-2D are plots 200 a-200 d of detected light intensity versus wafer position for the exemplary wafer alignment marks in FIG. 1A according to some embodiments. In FIG. 2A, the (light) intensity plot 200 a shows finding the position 1 of the first wafer alignment mark 104 a in FIG. 1A with one recess (opening, hole, or cut). As the wafer 102 is rotated 90 degrees, the detected light intensity is reduced at position 1 due to the first wafer alignment mark 104 a. Since the detected intensity is reduced one time, the position 1 is found as the first wafer alignment mark 104 a. The position 1 can be used for the wafer alignment. In some embodiments, a computer, a processor, or a memory can be used to monitor the detected intensity or save the position for alignment.

In FIG. 2B, the (light) intensity plot 200 b shows finding the position II of the second wafer alignment mark 104 b in FIG. 1A with two recesses. As the wafer 102 is rotated 90 degrees, the detected light intensity is reduced two times centered at the position II due to the second wafer alignment mark 104 b. The position II is found as the second wafer alignment mark 104 b. The position II can be used for the wafer alignment.

In FIG. 2C, the (light) intensity plot 200 c shows finding the position III of the third wafer alignment mark 104 c in FIG. 1A with three recesses. As the wafer 102 is rotated 90 degrees, the detected light intensity is reduced three times centered at the position III due to the third wafer alignment mark 104 c. The position III is found as the third wafer alignment mark 104 c. The position III can be used for the wafer alignment.

In FIG. 2D, the (light) intensity plot 200 d shows finding the position IV of the fourth wafer alignment mark 104 d in FIG. 1A with four recesses. As the wafer 102 is rotated 90 degrees, the detected light intensity is reduced four times centered at the position IV due to the fourth wafer alignment mark 104 d. The position IV is found as the fourth wafer alignment mark 104 d. The position IV can be used for the wafer alignment.

Even though the number of recesses is counted to find and identify wafer alignment marks 104 in the examples, different shapes or patterns comprising multiple small recesses can be used for the wafer alignment marks 104 with the light detection device 110 recognizing the shapes or patterns.

FIG. 3 is a schematic diagram of exemplary wafer alignment mark shapes according to some embodiments. FIG. 3 shows different wafer alignment mark shapes 302, 304, 306, and 308 comprising multiple small recesses or holes (dots). The light detection device 110 detects (identifies or recognizes) the shapes or patterns and find the alignment position in some embodiments. Any other shapes or patterns can be used for the wafer alignment marks 104 in FIG. 1A in other embodiments.

FIG. 4 is a flowchart of an exemplary method of wafer alignment using wafer alignment marks 104 in FIG. 1A according to some embodiments. At step 402, light is transmitted from a light source to a backside of a wafer. At step 404, the wafer is rotated for a specified angle, e.g., 90°. The rotated angle is 360° divided by the number of wafer alignment marks in some embodiments. In some embodiments, if the distribution of alignments marks is uneven, the specified angle is different than 360° divided by the number of wafer alignment marks. At step 406, reflected light from the backside of the wafer is detected by a light detection device. At step 408, a position of at least one wafer alignment mark that is formed on the backside of the wafer is found.

According to some embodiments, a wafer alignment apparatus includes a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide light directed to a backside of the wafer. The light detection device is configured to detect reflected light intensity from the backside of the wafer to find a position of at least one wafer alignment mark formed on the backside of the wafer.

According to some embodiments, a method includes transmitting light from a light source to a backside of a wafer. The wafer is rotated for a specified angle. Reflected light from the backside of the wafer is detected by a light detection device. A position of at least one wafer alignment mark formed on the backside of the wafer is found.

According to some embodiments, a wafer includes a front side used as a main surface for integrated circuit formation, a backside, and at least one wafer alignment mark formed on the backside. The at least one wafer alignment mark is configured to change a light intensity reflected from the backside in order to find a position of the at least one wafer alignment mark.

An aspect of this description relates to a wafer alignment apparatus. The wafer alignment apparatus comprises a light source, a light detection device, and a rotation device configured to rotate a wafer. The light source is configured to provide a light directed to the wafer. The light detection device is configured to detect reflected light intensity from the wafer to locate at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles. At least two of those angles are equal.

Another aspect of this description relates to a method comprising transmitting light from a light source to a wafer, rotating the wafer for a specified angle, detecting reflected light from the wafer by a light detection device, and locating at least one wafer alignment mark of wafer alignment marks separated by a plurality of angles, and at least two of those angles are equal.

A further aspect of this description relates to a wafer that has wafer alignment marks. At least one wafer alignment mark is configured to change a light intensity reflected from the wafer in order to locate the at least one wafer alignment mark. The wafer alignment marks are separated by a plurality of angles, and at least two of the angles are equal.

A skilled person in the art will appreciate that there can be many embodiment variations of this disclosure. Although the embodiments and their features have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosed embodiments, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure.

The above method embodiment shows exemplary steps, but they are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of embodiment of the disclosure. Embodiments that combine different claims and/or different embodiments are within the scope of the disclosure and will be apparent to those skilled in the art after reviewing this disclosure. 

What is claimed is:
 1. A semiconductor device comprising: a semiconductor wafer comprising a first side and a second side opposite the first side; active devices located adjacent to the first side; a first alignment mark in the second side, the first alignment mark comprising first recesses, wherein the first recesses change a light intensity reflected from the semiconductor wafer a first amount; and a second alignment mark in the second side, the second alignment mark comprising second recesses, the second recesses being identifiably different from the first recesses, wherein the second recesses change a light intensity reflected from the semiconductor wafer a second amount identifiably different from the first amount.
 2. The semiconductor device of claim 1, wherein the second alignment mark is located 90° away from the first alignment mark.
 3. The semiconductor device of claim 1, wherein the second alignment mark is located 120° away from the first alignment mark.
 4. The semiconductor device of claim 1, further comprising a third alignment mark comprising third recesses, the third recesses being identifiably different from the first recesses and the second recesses.
 5. The semiconductor device of claim 4, further comprising a fourth alignment mark comprising fourth recesses, the fourth recesses being identifiably different from the first alignment mark, the second alignment mark, and the third alignment mark.
 6. The semiconductor device of claim 5, where each one of the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark are located equally away from each other.
 7. The semiconductor device of claim 1, wherein the first alignment mark has a pyramidal shape.
 8. A semiconductor device comprising: a semiconductor wafer; a first set of recesses within the semiconductor wafer, wherein each recess within the first set of recesses is aligned with other recesses within the first set of recesses; and a second set of recesses within the semiconductor wafer, the second set of recesses having a different number of recesses from the first set of recesses, wherein each recess within the second set of recesses is aligned with other recesses within the second set of recesses.
 9. The semiconductor device of claim 8, wherein each recess within the first set of recesses is filled with a dielectric material.
 10. The semiconductor device of claim 8, wherein the first set of recesses is located 90° away from the second set of recesses.
 11. The semiconductor device of claim 8, wherein the first set of recesses has a pyramidal shape.
 12. The semiconductor device of claim 8, wherein the first set of recesses is located 120° away from the second set of recesses.
 13. The semiconductor device of claim 8, wherein the first set of recesses has a square shape.
 14. The semiconductor device of claim 8, wherein the first set of recesses has a first depth of about 0.12 μm.
 15. A semiconductor device comprising: a semiconductor wafer with a first quadrant, a second quadrant, a third quadrant, and a fourth quadrant; a first alignment mark located within the first quadrant; a second alignment mark located within the second quadrant; a third alignment mark located within the third quadrant; and a fourth alignment mark located within the fourth quadrant, wherein reflected light is identifiably different based on which of the first alignment mark, the second alignment mark, the third alignment mark, and the fourth alignment mark reflects the reflected light.
 16. The semiconductor device of claim 15, wherein the first alignment mark has a first depth of about 0.12 μm.
 17. The semiconductor device of claim 15, wherein the first alignment mark has a first depth of between about 100 nm and about 200 nm.
 18. The semiconductor device of claim 15, wherein the first alignment mark has a rectangular shape.
 19. The semiconductor device of claim 15, wherein the first alignment mark is located 90° away from the second alignment mark.
 20. The semiconductor device of claim 15, wherein the first alignment mark comprises a plurality of circular holes. 